The present invention is directed to compositions and methods for cleaning microelectronic structures. In particular, the present invention is directed to stripping silicon from complex substrate surfaces that comprise Si wafers, Through Silicon Vias (TSVs), and passivation layers. The silicon wafers may have resistivities that vary from 0.02 Ohm-cm to 100 ohm-cm. The TSVs are protected by typical passivation layers comprising TaN, SiN, TiN, and SiO2.
During the production of microelectronic devices, there are primarily three types of “interconnects” that are employed in the packaging process, wherein the silicon die interfaces with the “outside” world, as well as to other die. These are wire bonding, the use of bumps, and the use of TSVs. The third method involving the use of TSVs is the focus of this application. TSVs are used to attach a device to one or more functional devices or to attach multiple device types to a carrier.
The use of TSVs is a key manufacturing option to shrink device size based on 3D Integrated Circuits (ICs). TSVs are currently used in sensors but semiconductor manufacturing companies are starting to produce semiconductor devices such as 3D stacked DRAMs, and two or more devices in a very thin package that may be useful in mobile phones, for example. The manufacture of devices containing 3D memory and logic integrated in memory in a very compact structure is also the object of this invention.
TSV process steps add cost to the devices. A typical TSV process flow may include one or more of the following steps: (1) a wafer thinning step, (2) a Si etch method to make the TSVs, (3) one or more passivation steps by PECVD to act as baffler, (4) filling the TSV with copper; (5) a CMP step to thin the opposite side of the wafer etched in step (2); (6) a dry etch TSV reveal step using Si etchant gases, and (6) a wet cleans step to strip etch residues.
It is, therefore, highly desirable to provide Si etchant and/or stripping compositions that would replace the dry etch and wet cleans steps with an etchant solution that provides ones or more of the following benefits: has high Si etch rates, low passivation etch, low surface roughness for Si after wet etch, and exhibits high bath loading.